[Verilog] F/F 코드

D F/F with synchronous reset & CE

reset	ce	d	Q
0	0	0	q
0	0	1	q
0	1	0	0
0	1	1	1
1	x	x	0

 

module d_ff_ce_synch_reset(
    input d,
    input ce,
    input clk,
    input reset,
    output reg q
    );
    
    always @(posedge clk)
    begin
        if(reset)
        begin
            q <= 1'b0;
        end else if(ce)
        begin
            q <= d;
        end
    end
    
endmodule

 

 

T F/F with sync negative-logic reset & CE

n_reset	t	Q
0	x	0
1	0	q
1	1	~q

module t_ff(
    input t,
    input clk,
    input n_reset,
    output reg q
    );
    
    always @(posedge clk)
    begin
        if(!n_reset)
        begin
            q <= 1'b0;
        end else if(t)
        begin
            q <= ~q;
        end
    end
endmodule